Three-dimensional system in packaging (3D-SiP) technology is driven by the strong demand for high speed, high density, small size, and multifunctional electronic devices. Through-silicon via (TSV) interconnection is a way for 3D integration due to its shortest interconnection distance and fastest speed. To address the needs in Flip chip packaging technology, silicon (Si) interposer with TSV has emerged as a good solution to provide high writing density interconnection, minimize coefficient of thermal expansion (CTE) mismatch between the die and the interposer, and improve electrical performance due to short interconnection from chip to the substrate. There are several steps involved in TSV processes which could successfully address the limitations of packaging technologies, including via forming, sidewall insulating, via filling, wafer thinning and wafer/die stacking. TSV is electrically isolated from the substrate and from the other TSV connections by TSV sidewall insulation that also determines the TSV parasitic capacitance. To ensure the expected insulation properties with high breakdown voltage, no leakage, and no cracking, the TSV sidewall insulation needs good coverage and uniformity, lower stress, and process compatibility. However, traditional via etching process on silicon, via sidewall shows scallop-like shapes consisting of many micro-concaves, which can vary in size depending on process parameters. A series of etched “scallops” in the silicon causes uneven layer/dielectric layers and voids in the conductor-filled via. Sidewall insulation roughness is one of the challenging bottlenecks in TSV processes.